A Fast Locking Scheme for PLL Frequency Synthesizers A frequency synthesizer is described which employs a scheme for reducing lock time by a factor of two using a conventional phase locked loop architecture.

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Title of Site	Comments	Last Check
A Fast Locking Scheme for PLL Frequency Synthesizers	A frequency synthesizer is described which employs a scheme for reducing lock time by a factor of two using a conventional phase locked loop architecture.	2005-11-02
An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL’s	This application note investigates the design of passive loop filters for frequency synthesizers utilizing a phase-frequency detector and a current switch charge pump.	2005-11-02

Last Update: 2005-11-02